Session 1: Introduction to ASIC Design Flow

• Overview of ASIC Development Process
• Difference between ASIC, FPGA, and SoC Design
• Key terms: VLSI, RTL, HDL, Verification, Synthesis

Session 2: System Design & Architecture

• Product Requirement Document (PRD)

  • Market analysis, competitive positioning
  • Defining functional and non-functional requirements

• System Architecture

  • High-level block diagram of ASIC/SoC
  • Defining peripherals, memory, connectivity, and security modules

• Chip Architecture

  • Sub-system level design considerations
  • Clock, Reset, Power Domain, and Memory Management

Session 3: Front-End Design Flow

• High-Level Design (HLD)

  • Microarchitecture Definition (block diagrams, state machines)
  • Clocking scheme and performance considerations

• Low-Level Design (LLD) & RTL Coding

  • Writing RTL code using Verilog/VHDL
  • Data Path & Control Path Design
  • Coding guidelines for synthesis optimization

Session 4: ASIC Design Verification & Simulation

• Functional Verification Process

  • Creating a Test Plan (Module, Sub-System, and System Level)
  • Writing Testbenches & Stimulus Generation

• Formal Verification & Equivalence Checking

  • Verifying RTL vs. synthesized netlist
  • Static Timing Analysis (STA)

• Simulation & Debugging

  • Running test vectors on RTL models
  • Using Waveform Viewer (ModelSim, Questa, VCS)

Session 5: FPGA Prototyping & Pre-Silicon Validation

• FPGA Prototyping for ASIC Verification

  • Implementing RTL design on FPGA
  • Partitioning large designs across multiple FPGAs

• Hardware Emulation vs. FPGA Prototyping

  • When to use FPGA vs. Emulation vs. Gate-Level Simulation

• Challenges in ASIC Design Verification

  • Reducing simulation time
  • Improving verification coverage

Session 6: Case Study & Hands-on Lab

• Case Study: Mobile SoC Design & Verification
  • Translating PRD to System-Level Architecture
  • Defining clock & reset schemes
  • Writing a basic RTL module and verifying it using a testbench