Duration: 2 Days (14 Hours)
Level: Beginner to Intermediate
Course Overview
This course provides a refresher on digital design fundamentals and covers Register Transfer Level (RTL) design concepts and constructs. It includes both theoretical and practical sessions, enabling participants to design digital circuits, implement RTL models, and verify designs using Verilog testbenches.
Participants will learn how to convert digital systems into RTL code, implement Finite State Machines (FSMs), and understand timing constraints in digital design.
Learning Outcomes
By the end of this course, participants will:
Understand combinational and sequential circuit design.
Gain expertise in RTL design principles and coding constructs.
Convert digital systems into RTL code.
Design and implement basic Finite State Machines (FSMs).
Understand timing concepts and constraints in digital circuits.
Verify RTL designs using a Verilog-based testbench.
Who Should Attend?
VLSI & Hardware Engineers – Working on ASIC and FPGA design.
Embedded System Developers – Understanding hardware description languages.
Students & Beginners – Strengthening digital design and RTL programming.
FPGA Designers & Chip Architects – Learning Verilog RTL coding and testbench development.
Pre-requisites
Undergraduate-level understanding of digital design.
Programming skills (C programming knowledge is a plus).
Experience with text editors (gvim or any other editor).
Logical and analytical thinking skills.
Lab Setup Requirements
Software & Tools:
Xilinx Vivado 2018.3 or later
Hardware Requirements:
Windows 10 or 11 (64-bit) OR Linux (RHEL 8, CentOS 8, Ubuntu 18.04/20.04, 64-bit)
Minimum 8GB RAM
