Section: Day 2 – Verilog & RTL Coding (7 Hours) | RTL Design - 1

Section outline

Introduction to Hardware Description Languages (HDL)

VHDL vs Verilog – Key Differences

Verilog Coding Concepts

Lexical Conventions & Data Types

Operators & System Tasks

Modules & Ports – Designing Digital Circuits in Verilog

RTL Coding & Modeling Constructs

Always and Initial Blocks

Blocking vs Non-blocking Assignments

Timing Control & Sensitivity Lists

Design Verification & Testbenches

Verilog Constructs for Verification

Creating a Basic Testbench for Design Validation

Hands-on RTL Design Exercises

Combinational Circuits:

8:1 Multiplexer, Encoder, Decoder

Sequential Circuits:

D Flip-Flop, Up-Down Counter (with Set/Reset)

Finite State Machine (FSM) Implementation

Designing a 256x8-bit FIFO & Traffic Light Controller

Section outline