Section outline

• Select section Day 1 – Digital Design & RTL Basics (7 Hours)

  Day 1 – Digital Design & RTL Basics (7 Hours)

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  • Introduction to VLSI & Digital Design

    • Evolution of VLSI: MSI → LSI → VLSI
    • ASIC vs FPGA Circuits
    • Typical Design Flow

  • Number Systems & Boolean Algebra

    • Binary, Octal, Hexadecimal Representations
    • Boolean Algebra & Logic Simplification

  • Combinational Logic Design

    • Logic Gates (AND, OR, NOT, XOR, XNOR)
    • Multiplexers, Encoders, Decoders, Adders, Comparators

  • Sequential Logic Design

    • Flip-Flops (D, JK, T), Latches, Registers, Counters
    • FSM Design: Moore vs. Mealy Machines

  • Clocking & Reset Strategies

    • Synchronous vs Asynchronous Designs
    • Clocking Techniques & Synchronization
• Select section Day 2 – Verilog & RTL Coding (7 Hours)

  Day 2 – Verilog & RTL Coding (7 Hours)

  • Introduction to Hardware Description Languages (HDL)

    • VHDL vs Verilog – Key Differences

  • Verilog Coding Concepts

    • Lexical Conventions & Data Types
    • Operators & System Tasks
    • Modules & Ports – Designing Digital Circuits in Verilog

  • RTL Coding & Modeling Constructs

    • Always and Initial Blocks
    • Blocking vs Non-blocking Assignments
    • Timing Control & Sensitivity Lists

  • Design Verification & Testbenches

    • Verilog Constructs for Verification
    • Creating a Basic Testbench for Design Validation

  • Hands-on RTL Design Exercises

    • Combinational Circuits:
      • 8:1 Multiplexer, Encoder, Decoder
    • Sequential Circuits:
      • D Flip-Flop, Up-Down Counter (with Set/Reset)
    • Finite State Machine (FSM) Implementation
    • Designing a 256x8-bit FIFO & Traffic Light Controller