Duration: 3 Days (24 Hours)
Delivery Format: Instructor-led (Online Webinars + Hands-on Labs)
Course Overview
This course provides a fundamental understanding of RISC-V, an open-source Instruction Set Architecture (ISA). Participants will explore RISC-V architecture, core extensions, software toolchains, core design, security, and performance optimization. The training includes both theoretical sessions and hands-on labs using a platform with CVA6 as RV64I IP, AI/cybersecurity accelerators, AXI4 bus, DMA, and FPGA memory blocks.
Learning Outcomes
By the end of this course, participants will:
Understand the modular architecture of RISC-V and how it compares with x86 & ARM.
Work with RISC-V base ISA (RV32I & RV64I) and core extensions (M, A, F, D, C).
Set up and utilize the RISC-V software toolchain (GCC, LLVM, GDB).
Simulate and debug RISC-V applications using Spike & QEMU.
Learn basic core design, pipeline structure, and memory hierarchy.
Implement RISC-V security features, including privilege modes & secure boot.
Optimize RISC-V performance through memory & pipeline tuning.
Who Should Attend?
- Embedded Engineers & System Architects
- Hardware Designers working on RISC-V processors
- Software Developers working with RISC-V toolchains
- Security Professionals interested in RISC-V security fundamentals
Prerequisites
- Basic understanding of computer architecture & processor design.
- Familiarity with Linux & C programming (recommended).
Lab Setup Requirements
- RISC-V Development Environment (GCC, LLVM, GDB)
- Simulation Tools (Spike, QEMU)
- Embedded Platform (CVA6-based board, FPGA setup)
Teaching Methodology
Instructor-led theory sessions with interactive discussions.
Hands-on labs using RISC-V software & hardware tools.
Live debugging & performance tuning exercises.
