Section outline

• Select section Day 1: Introduction to RISC-V & ISA Extensions (8 Hours)

  Day 1: Introduction to RISC-V & ISA Extensions (8 Hours)

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  • H1: Introduction to RISC-V Architecture (Theory)

    • Overview of RISC-V ISA modularity
    • Comparison with x86 & ARM architectures
    • Understanding RISC-V's open-source ecosystem

  • H2: RISC-V ISA and Core Extensions (Theory)

    • Fundamentals of RV32I & RV64I ISAs
    • Introduction to M (Multiply/Divide), A (Atomic), F (Floating Point), D (Double Precision), C (Compressed) extensions
    • Practical applications & benefits of these extensions
• Select section Day 2: Software Toolchain & Core Design (8 Hours)

  Day 2: Software Toolchain & Core Design (8 Hours)

  • H1: RISC-V Software Toolchain & Development (Theory + Lab)

    • Overview of RISC-V compilers (GCC, LLVM)
    • Debugging with GDB (GNU Debugger)
    • Using Spike & QEMU for RISC-V simulation

  • Hands-on Lab: Compiling and debugging RISC-V programs

  • H2: Basic Core Design and Customization (Theory)

    • Basics of RISC-V core pipeline design
    • Understanding memory hierarchy & cache management
    • Custom instruction set design for specific applications
• Select section Day 3: Security & Performance Optimization (8 Hours)

  Day 3: Security & Performance Optimization (8 Hours)

  • H1: Security Fundamentals in RISC-V (Theory)

    • Privilege modes & access control
    • Secure boot & cryptographic extensions
    • Security strategies for embedded applications

  • H2: Performance Optimization Techniques (Theory + Lab)

    • Fundamentals of memory management
    • Pipeline optimizations for execution efficiency
    • Compiler optimizations for performance gains
    • 🔹 Hands-on Lab: Optimizing RISC-V execution with compiler flags