Hardware Design

Duration: 6 Days (48 Hours)
Level: Advanced

Course Overview

This course provides in-depth knowledge of RISC-V architecture, advanced core customization, memory management, AI/ML accelerators, and security features. Participants will gain expertise in RISC-V vector processing, formal verification, multi-core system design, and open-source core generation.

With hands-on labs and case studies, participants will learn hardware/software co-design, performance profiling, and security implementations using real-world RISC-V SoC environments.

Who Should Attend?

SoC Designers & Chip Architects – Customizing RISC-V cores and accelerators.
Embedded System Developers – Implementing AI/ML and cryptographic operations.
Hardware Engineers – Optimizing cache, memory, and performance in RISC-V.
Security & Verification Engineers – Ensuring ISA compliance and secure execution.

Why Choose This Course?

Covers RISC-V core customization, AI/ML integration, and security features.
Hands-on training using CVA6, AXI4, DMA, FPGA memory blocks.
Learn RISC-V performance optimization, profiling, and formal verification.

Hardware Design

Duration: 3 Days (24 Hours)
Delivery Format: Instructor-led (Online Webinars + Hands-on Labs)

Course Overview

This course provides a fundamental understanding of RISC-V, an open-source Instruction Set Architecture (ISA). Participants will explore RISC-V architecture, core extensions, software toolchains, core design, security, and performance optimization. The training includes both theoretical sessions and hands-on labs using a platform with CVA6 as RV64I IP, AI/cybersecurity accelerators, AXI4 bus, DMA, and FPGA memory blocks.

Learning Outcomes

By the end of this course, participants will:

Understand the modular architecture of RISC-V and how it compares with x86 & ARM.
Work with RISC-V base ISA (RV32I & RV64I) and core extensions (M, A, F, D, C).
Set up and utilize the RISC-V software toolchain (GCC, LLVM, GDB).
Simulate and debug RISC-V applications using Spike & QEMU.
Learn basic core design, pipeline structure, and memory hierarchy.
Implement RISC-V security features, including privilege modes & secure boot.
Optimize RISC-V performance through memory & pipeline tuning.

Who Should Attend?

• Embedded Engineers & System Architects
• Hardware Designers working on RISC-V processors
• Software Developers working with RISC-V toolchains
• Security Professionals interested in RISC-V security fundamentals

Prerequisites

• Basic understanding of computer architecture & processor design.
• Familiarity with Linux & C programming (recommended).

Lab Setup Requirements

• RISC-V Development Environment (GCC, LLVM, GDB)
• Simulation Tools (Spike, QEMU)
• Embedded Platform (CVA6-based board, FPGA setup)

Teaching Methodology

Instructor-led theory sessions with interactive discussions.
Hands-on labs using RISC-V software & hardware tools.
Live debugging & performance tuning exercises.

Hardware Design

Duration: 2 Days (14 Hours)
Level: Beginner to Intermediate

Course Overview

This course provides a refresher on digital design fundamentals and covers Register Transfer Level (RTL) design concepts and constructs. It includes both theoretical and practical sessions, enabling participants to design digital circuits, implement RTL models, and verify designs using Verilog testbenches.

Participants will learn how to convert digital systems into RTL code, implement Finite State Machines (FSMs), and understand timing constraints in digital design.

Learning Outcomes

By the end of this course, participants will:

Understand combinational and sequential circuit design.
Gain expertise in RTL design principles and coding constructs.
Convert digital systems into RTL code.
Design and implement basic Finite State Machines (FSMs).
Understand timing concepts and constraints in digital circuits.
Verify RTL designs using a Verilog-based testbench.

Who Should Attend?

VLSI & Hardware Engineers – Working on ASIC and FPGA design.
Embedded System Developers – Understanding hardware description languages.
Students & Beginners – Strengthening digital design and RTL programming.
FPGA Designers & Chip Architects – Learning Verilog RTL coding and testbench development.

Pre-requisites

Undergraduate-level understanding of digital design.
Programming skills (C programming knowledge is a plus).
Experience with text editors (gvim or any other editor).
Logical and analytical thinking skills.

Lab Setup Requirements

Software & Tools:

Xilinx Vivado 2018.3 or later

Hardware Requirements:

Windows 10 or 11 (64-bit) OR Linux (RHEL 8, CentOS 8, Ubuntu 18.04/20.04, 64-bit)
Minimum 8GB RAM