Section outline

• Select section Day 1 – RISC-V Core Customization & Vector Processing

  Day 1 – RISC-V Core Customization & Vector Processing

  Collapse all Expand all

  • Session 1: Advanced Core Customization & Design

    • Designing specialized RISC-V cores with custom instruction sets
    • Pipeline optimizations for specific applications
    • Building application-specific accelerators

  • Session 2: RISC-V Vector Processing & SIMD Extensions

    • RISC-V Vector Extension (RVV) and its configuration
    • SIMD processing for high-performance computing
    • Vector operations for AI/ML and data-intensive applications
• Select section Day 2 – Hardware/Software Co-Design & Verification

  Day 2 – Hardware/Software Co-Design & Verification

  • Session 1: Hardware/Software Co-Design for RISC-V (Theory + Hands-on Lab)

    • Techniques for hardware-software integration in RISC-V SoCs
    • Optimizing co-processors and accelerators
    • Case studies in co-design for high-performance applications

  • Session 2: Formal Verification & Compliance for RISC-V (Theory + Hands-on Lab)

    • Formal verification methods for ensuring ISA compliance
    • Using open-source verification frameworks for RISC-V cores
    • Ensuring functional correctness through verification
• Select section Day 3 – Memory Management & Multi-Core RISC-V Systems

  Day 3 – Memory Management & Multi-Core RISC-V Systems

  • Session 1: Memory Management & Advanced Cache Optimization

    • Memory hierarchy design & MMU implementation
    • Cache design & coherence models
    • Optimizing memory for virtual memory operations

  • Session 2: Multi-Core & Heterogeneous RISC-V Systems

    • Designing multi-core RISC-V architectures
    • Synchronization techniques in multi-core systems
    • Integrating RISC-V with other architectures
• Select section Day 4 – Advanced Security Features in RISC-V

  Day 4 – Advanced Security Features in RISC-V

  Session 1 & 2: RISC-V Security Architecture

  • Secure Boot Implementation & Trusted Execution Environments
  • Cryptographic operations with P (Packed SIMD) and B (Bit Manipulation) extensions
  • Enhancing security for data centers & IoT devices
  • Verification techniques for RISC-V security
• Select section Day 5 – AI/ML Acceleration & Performance Optimization

  Day 5 – AI/ML Acceleration & Performance Optimization

  • Session 1: RISC-V for AI & Machine Learning

    • Designing AI/ML accelerators in RISC-V
    • Optimizing neural networks & inference engines
    • Case studies of RISC-V applications in AI & ML

  • Session 2: Advanced Performance Profiling & Optimization (Theory + Hands-on Lab)

    • Profiling RISC-V performance using tools
    • Advanced compiler optimizations & tuning
    • Using performance counters & monitoring tools
• Select section Day 6 – RISC-V Ecosystem & Open-Source Core Generators

  Day 6 – RISC-V Ecosystem & Open-Source Core Generators

  Session 1 & 2: Exploring the RISC-V Ecosystem (Theory + Hands-on Lab)

  • Introduction to CVA6, Rocket, and BOOM cores
  • Customizing & generating RISC-V cores using open-source tools
  • Hands-on RISC-V core customization on CVA6
  • Collaborating with the open-source RISC-V community