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Section outline

    • Session 1: Hardware/Software Co-Design for RISC-V (Theory + Hands-on Lab)
      • Techniques for hardware-software integration in RISC-V SoCs
      • Optimizing co-processors and accelerators
      • Case studies in co-design for high-performance applications
    • Session 2: Formal Verification & Compliance for RISC-V (Theory + Hands-on Lab)
      • Formal verification methods for ensuring ISA compliance
      • Using open-source verification frameworks for RISC-V cores
      • Ensuring functional correctness through verification