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Section outline

    • Session 1: Memory Management & Advanced Cache Optimization
      • Memory hierarchy design & MMU implementation
      • Cache design & coherence models
      • Optimizing memory for virtual memory operations
    • Session 2: Multi-Core & Heterogeneous RISC-V Systems
      • Designing multi-core RISC-V architectures
      • Synchronization techniques in multi-core systems
      • Integrating RISC-V with other architectures